The power and current carrying capabilities of power switches such as MOSFETs and IGBTs are commonly limited by their package. Thus, the package introduces thermal and electrical resistance that can cause power loss and corresponding heating of the semiconductor die beyond its specified limits.
Beside the thermal issues, package inductivity is also an important limiting factor for switching high currents. Parasitic package inductance causes inductive over-voltage that can destroy the die. Such die may be silicon or GaN based die. This is especially true for state-of the art packaging technologies using bond wires for the electrical connection of the top-metals of the die to a lead frame or other external metal terminals. In order to take the inductive overvoltage into account the die used often must have a much higher breakdown voltage then the application itself would require.
Therefore, packaging technologies try to achieve low inductivity and better thermal connectivity to a heatsink by bond wireless connection techniques for the power devices. One example of such an approach is the DirectFET technology shown, for example, in U.S. Pat. No. 6,624,522 (IR-1830). By connecting the topside of the power die particularly the source or the emitter contact of a MOSgated device to a larger metal area, the package gains a higher current carrying capability, better thermal properties and a lower inductivity at the same time. (The top power electrode with hereinafter frequently be referred to as the source for both MOSFETs and IGBTs.) Other techniques use flip-chip soldering of the device or large metal straps are soldered on top of the die (source or emitter contact) in order to improve the thermal and electrical behavior of the device.
A major problem of large metal contacts or copper straps is the stress on the die due to the higher thermal expansion coefficient of metal compared to that of the die, such as a silicon based die. This may be acceptable in relatively moderate power applications as in consumer electronics but it creates a severe reliability issue for heavy duty applications in a harsh environment like those of automotive electronics. The stress effect in such extreme applications can cause major damage to the sensitive top metal layers of the die due to the active layers underneath.
Besides the introduced stress on the die, large metal contacts such as those used in a copper strap device or in the DirectFET device can metal, can have another disadvantage on the long term behavior of the package. Thus, the solder joint between the die and the metal contact tends to deteriorate rapidly if major temperature changes and cycling are applied. This failure mechanism is also driven by the thermal mismatch and the different thermal expansion of the metal contact vs. the die material. This results in micro cracks and even de-lamination of the contact, causing an increase of thermal and electrical resistance within the solder joint. Consequently, the package performance will be impacted.
Therefore the metal can of the DirectFET device uses an adhesive layer rather than a solder for the die attach of the backside of the die to the interior of the metal can in order to compensate the thermal expansion mismatch between die and metal can. Adhesives can deal better with stress induced forces and do not deteriorate like solder due to their higher flexibility. However, an adhesive or glue layer has limited current carrying capability and a higher thermal resistance as compared to solder.
Due to the above described thermal mismatch problems high power packages commonly use substrates like Direct-Bonded-Copper (DBC), which offers a better match of the thermal expansion coefficient to die substrates such as silicon. A DBC substrate generally comprises a central insulation layer, frequently a ceramic which has top and bottom conductive layers on its top and bottom surfaces. These are frequently copper. The top layer may be patterned as desired. This technology is normally used by soldering one side of a die to the top conductive layer of DBC while the other side is contacted via conventional wire bonds. As far as cooling is concerned, only one side of the die is cooled, while the other side suffers from the thermal bottleneck of the wirebonds. Further, the inductance is relatively high due to the wirebonds. Therefore, while DBC-substrate technology on one die side only solves the reliability problem, does not offer the best thermal and low-inductance performance.
It is known to use two DBC substrates, forming a sandwich of a top and a bottom DBC substrate and central die. The DBC substrates are relatively large since they also provide the whole circuitry for the power modules such as half-bridge-, H-bridge- or full-bridge configurations. Bare die are soldered between the top and bottom DBC. Bond-wireless die attach, low inductivity and both-sided cooling is thus addressed. The main disadvantage of these structures is the high cost of using two highly customized DBC substrates (since they provide the circuitry) which have to be extremely precise and flat since several bare die of a thickness of 100-300 μm need to be contacted between the substrates. This requires extreme precision which is a major challenge for production. Therefore, the high costs and manufacturing challenges for such a DBC sandwich technology are major obstacles for this technique.
A further disadvantage of the prior art packages described above is the difficulty of adding current sensing and over current sensing functions to the package. Thus, it is known to implement current measurement sensors into the application of such packages. These sensors allow a protection circuit to detect dangerous current limits and start countermeasures such as shutting down a system, limiting the current, running the application at lower performance by derating current or voltage and the like. These current sensors are normally resistors which are mounted in a current path of the application. Such current sensors introduce additional costs and need mounting space. Current sensing capabilities can also be added to the power device itself. Thus, current sense are known MOSFETs in which a small part of the current carrying area of the die is used to measure the current flow and determine, via calibration techniques which are well known, the corresponding full current through the full active area of the device. The disadvantages of this method are:                it needs additional space on the die;        it is relatively inaccurate, and especially;        it requires a special die design/layout.        
Another disadvantage regarding packaging of such current sensing power devices is that the current sense function needs at least two more contact pads which deliver a voltage signal proportional to the main current flow. These contacts are normally small low power pads connected via wire bonds to the external circuitry. Those contact pads reduce the available die surface further. Thus, the bond wireless power package becomes much more complex since two more small contacts need to be contacted, and bumping of the die becomes more complicated, too.
Another further disadvantage is the difficulty of testing/probing of die with integrated current sense functions. The current sense option adds test time and can reduce the yield of the wafer to due failures of the current sense cells.
However, motor drives, DC/AC—inverter or DC/DC converters using power switches in a half-, full- or H-bridge configuration need to measure and control the current very precisely. It is important that the corresponding control units get a precise feedback of the main current (e.g. the phase currents in a motor drive application). For these purposes sensors with relatively high accuracy are required (often over a large dynamic range). It is therefor to use highly precise shunt resistors, hall-sensors, magneto resistive sensors, and the like for this kind of current sensing.